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Syllabus: Sequential Circuits: Latches and flip-flops, counters, shift-registers, finite state machines, propagation delay, setup and hold time, critical path delay.
10 hand-picked visual resources on this topic, 1 of them little-known gems — under each card, look for See it. Every link is checked against the live site before it ships.
Flip-flop characteristic equations
Writing the next-state equation is usually faster than tracing waveforms round a state diagram.
D flip-flop
T toggles when
JK;
Counters and dividers
Each toggling stage halves the frequency. A JK flip-flop with both inputs high is a divide-by-two, so of them divide by .
Setup, hold and critical path
The maximum clock rate is set by the longest combinational path between two registers, plus the flip-flop's own delays.
Shift registers, ring and Johnson counters
An -bit shift register takes clocks to load or unload serially. The two counters built from one differ only in what is fed back: the plain output gives states, the inverted output gives .
Finite state machines: Moore and Mealy
In a Moore machine the output depends on the state alone, so it changes only on a clock edge and lags the input by one cycle. In a Mealy machine the output depends on state and input, so it responds a cycle earlier but can glitch when the input does.
cascaded toggle stages
flip-flops needed
regardless of the input duty cycle
See it
critical path
pipelining trades latency for throughput
See it
clocks for whichever side is serial.
one-hot, needs a preset to start
self-starting only with correction logic
the all-zero state is excluded and is a lock-up
Where marks are lost
A ring counter uses flip-flops for states where a binary counter needs only . It is chosen for the decoded, glitch-free one-hot output, never for efficiency.
See it
binary encoding; one-hot uses one per state and simpler next-state logic
Moore often needs extra states purely to hold an output.
Two states are equivalent if they give the same outputs and go to equivalent next states — state reduction by implication table.
the next-state logic sits on the critical path
Where marks are lost
Moore outputs are registered and therefore safe to use as control signals; Mealy outputs are combinational and can glitch mid-cycle. A question about a spurious output is almost always about a Mealy machine.