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Syllabus: Data Converters: Sample and hold circuits, ADCs and DACs. Semiconductor Memories: ROM, SRAM, DRAM. Computer Organization: Machine instructions and addressing modes, ALU, data-path and control unit, instruction pipelining.
10 hand-picked visual resources on this topic, 1 of them little-known gems — under each card, look for See it. Every link is checked against the live site before it ships.
ADC resolution and SNR
Each extra bit buys about 6 dB. The same relation run backwards turns a measured SINAD into an effective number of bits.
full-scale sinusoid
step size
fast but expensive
See it
Instruction field sizing
Count the bits each field needs, always rounding up, and whatever remains of the word belongs to the immediate.
SRAM vs DRAM
SRAM holds its value in a latch, is fast, and needs no refresh; DRAM stores charge on a capacitor, is dense and cheap, and must be refreshed.
SRAM needs no refresh and is used for cache; DRAM does, and is main memory.
DACs
R-2R is the ladder that gets built, because it needs only two resistor values however many bits there are — weighted-resistor DACs need different values matched to within half an LSB, which is impossible past a few bits.
Sample-and-hold, and ADC architectures
An ADC needs its input to stop moving while it converts, and a sample-and-hold is what stops it. The requirement is hard: the input must not change by more than half an LSB during the conversion, which for a fast signal is a far tighter constraint than the sampling theorem.
Addressing modes, datapath and pipelining
The datapath does the work and the control unit tells it when; pipelining overlaps the two so a new instruction starts before the last has finished. The speed-up is never quite the number of stages, because the pipeline has to fill and then keeps stalling.
Addressing modes: immediate, register, direct, indirect, register-indirect, indexed, relative. The last two compute an effective address.
per register field
unsigned, leftover bits
= the input word as an integer
the step as a fraction of full scale
full-scale output is one LSB short of
a DAC is fast because it is not iterative — unlike an SAR ADC
Where marks are lost
Resolution is not accuracy. A 12-bit DAC with 1% gain error resolves 1 part in 4096 and is still wrong by 40 LSB at full scale.
See it
the whole reason a sample-and-hold is needed at all
for a full-scale sinusoid on an -bit converter
a bigger hold capacitor droops less but acquires more slowly
fastest, and the reason nobody builds a 12-bit flash
conversion time independent of the input value
Slow, but dual-slope rejects mains hum and is insensitive to drift.
Where marks are lost
Flash is in hardware and in time; SAR is the reverse. A question giving a conversion time and asking which architecture it is, is testing exactly that trade.
the usual counting question
the slowest stage sets the clock for all of them
stages, instructions — cycles of fill
speed-up over a non-pipelined machine
structural, data (RAW) and control hazards each add stalls
Where marks are lost
Splitting a pipeline into more stages shortens the clock but adds latch overhead and lengthens the branch penalty. Past a point the deeper pipeline is slower, which is why stage counts stopped growing.